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Date:  Thu, June 12, 2014
Time:  6:15 PM to 7:30 PM
Location:  POST Bldg, Room # 126
Speaker:  Dr. Subramaniam Iyer, IBM Fellow at the Systems & Technology Group, and Director, System Scaling Technology Function at IBM Microelectronics

Sponsored by University of Hawaii IEEE Student Branch and IEEE Hawaii 

As conventional device scaling slows to a grinding halt driven primarily by increased development and manufacturing costs with saturating returns, computing is experiencing a paradigm shift characterized by highly associative and contextual environments, approximate or probabilistic computations and very adaptive or dynamic structures. Such machines will likely be hybrids of both von Neumann machines as well as those with a more cognitive character. In this new era of hugely parallel and highly connected simple cores the role of packaging and non-traditional silicon processing such as 3 Dimensional integration, including heterogeneous integration will be paramount. I call this orthogonal scaling. We will examine in detail the challenges ahead in the areas of packaging and 3-Dimensional integration and suggest a global roadmap as we enter this new era of computing. Specifically, using memory as a paradigm, we will address the issue of scaling the package and the board as means to improve the cost-power-performance tradeoffs and argue that significant gains can be achieved through novel system integration constructs in spite of the saturation of "classical" silicon scaling.

Biography:

Subramanian S. Iyer is an IBM Fellow at the Systems & Technology Group, and directs the System Scaling Technology Function at IBM Microelectronics. He obtained his B.Tech. at IIT-Bombay, and Ph.D. at UCLA. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBM’s development partners. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 200 papers and holds over 65 patents. His current technical interests and work lie in the area of packaging and three-dimensional integration for system level scaling, as well as the long-term semiconductor and packaging roadmap for logic and memory. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.

For more information please visit: https://meetings.vtools.ieee.org/meeting_view/list_meeting/26603