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Date:  Fri, January 23, 2026
Time:  4:30pm - 6:00pm
Location:  Holmes Hall 389
Speaker:  Dr. Alvin Loke, Intel Corporation

Hosted by the IEEE Hawaii Section Jt. Chapter, ED15/SSC37

Please register at: https://events.vtools.ieee.org/m/518258

ECE Graduate Students: This will count towards your seminar credit.

Abstract:

Embrace the technology – the essence of how analog design has adapted and thrived throughout decades of increasingly unfriendly CMOS scaling.  This presentation will cover the impact of advanced CMOS on analog design, and examples of the creativity of analog designers to preserve and extend the performance of traditional analog functions. We will finally take a look at technologies on the horizon and suggest how they will impact the future of analog design.

Biography:

Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel’s gate-all-around CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. Alvin received a BASc from the University of British Columbia, and MS and PhD from Stanford. After several years in CMOS process integration, he has since worked on analog/mixed-signal design focusing on a variety of wireline links including chiplet IOs, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary, SSCS Global Chapters Chair, and again as SSCS Distinguished Lecturer. Alvin frequently speaks on CMOS technology and its impact on analog design, having authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC, VLSI Symposium, CICC, and BCICTS.